1. Field of the Invention
The present invention relates an A/D conversion device, and more particularly, to an A/D conversion device capable of switching between a comparator function and an A/D conversion function in a system that performs a feedback control with respect to an analog input within a specified range.
2. Description of Related Art
As response times for an embedded-type control become faster, there is a demand for a high-speed A/D conversion device. Especially in the field of motor control, there is an increasing demand for shortening a processing time from sensing of an analog output, such as position information or a current value output from a motor, to execution of a feedback control.
To achieve a reduction in A/D conversion time, there is disclosed an A/D conversion device capable of switching between a comparator function and an A/D conversion function (e.g., see Japanese Unexamined Patent Application Publication No. 61-125231). FIG. 5 is a block diagram showing the configuration of the A/D conversion device according to a prior art disclosed in Japanese Unexamined Patent Application Publication No. 61-125231.
Referring to FIG. 5, reference numeral 108 denotes a holding register, and reference numeral 107 denotes a shift register that sets a predetermined value to the holding register 108 at each clock input. Reference numeral 109 denotes a three-output (three-state) buffer that receives an output from the holding register 108. Reference numeral 111 denotes a reference supply of a D/A converter 110. Reference numeral 112 denotes a comparator that receives an analog output signal from the D/A converter 110 and an analog signal to be measured, and outputs a comparison result to the holding register 108. The shift register 107, the holding register 108, the three-output (three-state) buffer 109, the D/A converter 110, the reference supply 111, and the comparator 112 constitute a main part of the A/D conversion device.
Reference numeral 106 denotes an 8-bit microcomputer that controls the main part of the A/D conversion device. After A/D conversion is completed, ports P0.0 to P0.7 of the microcomputer 106 receive digital values held in the holding register 108, and directly output predetermined digital values to the D/A converter 110. A port P1.1 outputs a signal indicating the start of the A/D conversion, to each of the shift register 107 and the holding register 108. A port P1.2 receives an A/D conversion end signal from the holding register 108. A port P1.3 outputs a control signal to the three-output buffer 109. A port P1.0 receives an output from the comparator 112.
The main part of the A/D conversion device of the prior art configured as described above allows the three-output buffer 109 to operate normally, thereby enabling A/D conversion of a sequential comparison type.
The A/D conversion device of the prior art shown in FIG. 5 can also be operated as a digital comparator in the following manner. That is, first, the signal from the port P1.3 of the microcomputer 106 places the three-output buffer 109 into a floating state, and predetermined set values are output from the ports P0.0 to P0.7 to the D/A converter 110. The set values are subjected to D/A conversion by the D/A converter 110, and set analog values thus obtained are input to the plus terminal of the comparator 112. Then, the comparator 112 compares the set analog values with a measured analog value Vin and outputs a comparison result to the port P1.0 of the microcomputer 106. The microcomputer 106 checks whether the value input to the port P1.0 is “High” or “Low”, thereby making it possible to compare the measured analog value Vin with the set analog values.
Thus, in the A/D conversion device of the prior art, comparison and determination of the measured analog value Vin are made with respect to a threshold by using the comparator function. After that, the comparator function is switched to the A/D conversion function to convert an analog value into a digital value, thereby achieving a reduction in processing time required for the A/D conversion. Specifically, when a digital value of 2 V or greater among analog inputs within a range of 0 V to 5 V is required, for example, the need for processing to determine whether the analog input is equal to or higher than 2 V and to convert an analog value into a digital value every time the analog input is lower than 2 V is eliminated.
Meanwhile, Japanese Unexamined Patent Application Publication No. 56-13830 discloses a technique that has the effect of eliminating noise in an A/D conversion device, though the technique does not involve A/D conversion of an analog voltage higher than a threshold, unlike the technique disclosed in Japanese Unexamined Patent Application Publication No. 61-125231. According to the technique disclosed in Japanese Unexamined Patent Application Publication No. 56-13830, a previous A/D conversion result is stored, and when an analog voltage to be subjected to A/D conversion falls within a desired range, noise elimination is carried out without performing any A/D conversion operation. This results in a reduction in waste of the A/D conversion time. The technique disclosed in Japanese Unexamined Patent Application Publication No. 56-13830 has a drawback in that, when excessive noise occurs, it is necessary to perform A/D conversion four to eight times in order to restore the normal and stable operation.